The present invention is related to ball grid array packages. More specifically, the present invention relates to methods and apparatus for forming a more co-planar structure for ball grid array packages.
The semiconductor industry has seen tremendous advances in technology in recent years that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second), to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages that receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
In the past, the die and package were first attached and then were wire bonded. In a wired bonded die and package, a thin (0.7 to 1.0 mil) wire is bonded to the chip bonding pad, and spanned to the inner lead of the package lead frame. Next, the wire is bonded to the inner lead. Lastly, the wire is clipped and the entire process repeated at the next bonding pad. Wire bonding between a die and a package has several problems. One problem is that a wire bond attachment to a die limits the number of pads and placement of the pads on the die. In addition, minimum height limits are imposed by the required wire loops. Another problem is that there is a chance of electrical performance problems or shorting if the wires come too close to each other. The wire bonds also require two bonds, and must be placed one-by-one, and there are resistances associated with each bond. The wires are also relatively long.
To increase the number of pad sites available for a die and to overcome other problems, dies were provided with deposited metal bumps on each bonding pad. The bonding pads were also moved to the side of the die nearest the transistors and other circuit devices formed in the die. As a result, the electrical path to the pad is shorter. Connection to the package is made when the chip is flipped over and soldered. As a result, the dies are commonly called flip chips in the industry. Each bump connects to a corresponding package inner lead. The packages which result are lower profile and have lower electrical resistance and a shortened electrical path. The plurality of ball-shaped conductive bump contacts (usually solder, or other similar conductive material) are typically disposed in a rectangular array. The packages are occasionally referred to as xe2x80x9cBall Grid Arrayxe2x80x9d (BGA) or xe2x80x9cArea Grid Arrayxe2x80x9d packages, or Chip Size Packages (CSPs).
A typical BGA package is characterized by a large number of solder balls disposed in an array on a surface of the package. It is not uncommon to have hundreds of solder balls in an array. The BGA package is assembled to a matching array of conductive pads. The pads are connected to other devices within a substrate or circuitry on a circuit board. Heat is applied to reflow the solder balls (bumps) on the package, thereby wetting the pads on the substrates and, once cooled, forming electrical connections between the package and the semiconductor device contained in the package and the substrate.
The introduction of flip chips and Ball Grid Array (BGA) packages to the semiconductor industry have brought several new manufacturing and assembly challenges. One of the more significant challenges is keeping the height of solder ball contacts substantially uniform or substantially co-planar. This is a critical factor for successful attachment of BGA-type packages to mother boards. If one or more balls are significantly shorter than others, it becomes highly likely that these smaller (shorter) contacts will completely miss their mating contact pads and will fail to form an electrical connection between the semiconductor package and the mother board. Manufacturers must meet standard specifications regarding co-planarity. One common standard is JEDEC, which sets the maximum acceptable ball co-planarity for any size package to be 8 mils. The maximum height difference between the balls in the array is known as the co-planarity of the substrate.
Another challenge is to control the volume of solder associated with each pad. If one pad is provided with too much solder, it may contact a neighboring pad on the land side of the package, causing an unwanted contact or short in the package.